Joint Event with SSCS & ITS : Shannon-inspired Statistical Computing

Friday, February 27th, 2015 at 4:30 PM to 6:30 PM

Jack Gifford Event Center at Maxim Integrated Headquarters (160 Rio Robles, San Jose, CA 95134 USA)


4:30 - 5:00 PM Networking & Refreshments
5:00 - 6:30 PM Talks & Adjournment

Organizer: IEEE SCV SSCS & ITS

Session Abstract:-Eventbrite registration is mandatory for every one to attend the talk.

Speaker: Dr. Naresh R. Shanbhag

Bio: Naresh R. Shanbhag is the Jack Kilby Professor of Electrical and Computer Engineering in the Department of Electrical and Computer Engineering at the University of Illinois at Urbana-Champaign. His research interests are in the design of robust and energy-efficient integrated circuits and systems for communications including VLSI architectures for error-control coding, and equalization, noise-tolerant integrated circuit design, error-resilient architectures and systems, and system-assisted mixed-signal design. Dr. Shanbhag received the 2010 Richard Newton GSRC Industrial Impact Award, became an IEEE Fellow in 2006, received the 2006 IEEE Journal of Solid-State Circuits Best Paper Award, the 2001 IEEE Transactions on VLSI Best Paper Award, the 1999 IEEE Leon K. Kirchmayer Best Paper Award, the 1999 Xerox Faculty Award, the Distinguished Lecturership from the IEEE Circuits and Systems Society in 1997, the National Science Foundation CAREER Award in 1996, and the 1994 Darlington Best Paper Award from the IEEE Circuits and Systems Society.

Title: Shannon-inspired Statistical Computing

Abstract: -Moore's Law has been the driving force behind the exponential growth in the semiconductor industry for the past five decades. Today, energy efficiency and reliability challenges in nanoscale CMOS (and beyond CMOS) processes threaten the continuation of Moore's Law. This talk will describe our work on developing a Shannon-inspired statistical information processing that seeks to address this issue by treating the problem of computing on unreliable devices and circuits as one of information transfer over an unreliable/noisy channel. Such a paradigm seeks to transform computing from its von Neumann roots in data processing to Shannon-inspired information processing. Key elements of this paradigm are the use of statistical signal processing, machine learning principles, equalization and error-control, for designing error-resilient on-chip computation, communication, storage, and mixed-signal analog front-ends. The talk will provide a historical perspective and demonstrate examples of Shannon-inspired designs of on-chip subsystems. This talk will conclude with a brief overview of the Systems On Nanoscale Information fabriCs (SONIC) Center, a multi-university research center based at the University of Illinois at Urbana-Champaign, focused on developing a Shannon/brain-inspired foundation for information processing on CMOS and beyond CMOS nanoscale fabrics.